This invention relates to CMOS integrated circuit fabrication processes, and specifically to a process for forming a SiGe heterojunction bipolar transistor BiCMOS on a silicon-on-insulator substrate. Such a structure is particularly suited for use in high-speed, mixed-signal circuits.
The prior art describes the construction of a of SiGe bipolar CMOS (BiCMOS) by fabricating a SiGe heterojunction bipolar transistor (HBT) and a CMOS on a bulk silicon substrate. This process produces a very high performance HBT, for analog signal processing, and a CMOS, for digital signal processing and data storage. A significant problem with such structure is that the bulk CMOS is relatively slow and requires a relatively high power input. The fabrication process is relatively complex, and the resulting product is not suitable for hand-held wireless devices, because of its power requirements. By integrating a SiGe HBT and CMOS onto a silicon-on-insulator (SOI) substrate, the performance of the SiGe HBT and the low power, high-speed properties of SOI CMOS devices may be achieved in a single structure. The SiGe HBT provides a high-speed front-end transceiver and the CMOS provides data processing and storage.
A semiconductor structure includes, on a SOI substrate, a CMIOS formed on the substrate; and a SiGe HBT formed on the substrate. A method of fabricating a semiconductor structure includes preparing a SOI substrate having plural active regions thereon; forming a CMOS on the SOI substrate in a first active region; and forming a SiGe HBT on the SOI substrate in another active region.
An object of the invention is to provide a inixed-signal processing structure which has relatively low power consumption.
Another object of the invention is to provide a high performance SiGe heterojunction bipolar transistor BiCMOS on a silicon-on-insulator substrate.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.